The present invention relates to a field-effect semiconductor device and, more particularly, to a field-effect semiconductor device formed on an insulating layer and a method of manufacturing the same.
FIG. 3 shows an example of a conventional field-effect semiconductor device. Referring to FIG. 3, reference numeral 1 denotes a monocrystalline silicon substrate; and 2, an insulating layer formed on this semiconductor substrate. This insulating layer 2 is an insulating film such as a silicon oxide film for electrically insulating an active layer 3 formed on the insulating layer 2 and having a first conductivity type, e.g., a p type from the monocrystalline semiconductor substrate 1. Reference numeral 4 denotes a gate insulating film such as a silicon oxide film; 5, a source region of a second conductivity type, e.g., an n type; and 6, a drain region of the second conductivity type, i.e., the n type. The source region 5, the active layer 3, and the drain region 6 are arranged adjacent to each other in the order named on the insulating film 2. Reference numeral 7 denotes a gate electrode arranged on the gate insulating film 4 corresponding to the active layer 3; 8a, 8b, and 8c, insulating films to electrically insulate interconnecting layers; 9, a source electrode; and 10, a drain electrode.
In a semiconductor device of this type, the impurity concentration of the active layer 3 is designed such that the thickness of a depletion layer which may expand from the gate electrode side is larger than a thickness t.sub.0 of the active layer 3, and consequently the entire region of the active layer is depleted when the semiconductor device is in operation. The reasons for this arrangement are: (1) the mobility deterioration of carriers at inverted surface immediately below the gate insulating film 4 can be suppressed by reducing the effective electric field strength in the active layer, and thereby the drain current can be increased, and (2) the drain current can increase with an increase in carriers at inverted surface in the active layer, corresponding to a reduction in a charge amount in the depletion layer formed. In addition, in a semiconductor device having the above arrangement, since the active layer 3 is depleted by a gate-induced electric field, it is possible to suppress an incursion of a drain electric field from a drain junction into the active layer 3, and in this manner the short channel effect in a threshold voltage can be suppressed. Accordingly, a semiconductor device of this type is expected to realize both a high-density integration of a semiconductor device obtained by down scaling in dimensions and a high-speed operation and therefore has attracted attention as a promising device in recent years.
FIGS. 4A to 4E show a practical example of a method of manufacturing the semiconductor device shown in FIG. 3.
First, as shown in FIG. 4A, a silicon oxide film 2 is buried in, e.g., a monocrystalline silicon semiconductor 1, and a first silicon semiconductor layer 11 is formed on the silicon oxide film 2, thereby preparing a silicon semiconductor structure. This semiconductor structure is formed by implanting oxygen ions into, e.g., a monocrystalline semiconductor.
Subsequently, as shown in FIG. 4B, the first semiconductor layer 11 on the major surface side of the semiconductor structure is formed into predetermined dimensions by, e.g., an anisotropic plasma etching technique, thus forming a silicon semiconductor layer 11.sub.1.
As shown in FIG. 4C, a predetermined impurity is doped into the silicon semiconductor region 11.sub.1 by, e.g., an ion-implantation technique to form an active layer 3 of a first conductivity type (p type). Thereafter, a silicon oxide film 4 as a gate insulating film, for example, is formed on the active layer 3, and subsequently a doped silicon layer 12, for example, as a gate electrode is deposited.
As shown in FIG. 4D, the gate electrode silicon layer 12 is formed into predetermined dimensions by, e.g., the anisotropic plasma etching technique to form a gate electrode 7. Thereafter, a source region 5 of a second conductivity type (n type) and a drain region 6 of the same conductivity type are formed by, e.g., the ion-implantation technique. An insulating film 8, such as a silicon oxide film, is deposited on the major surface side of the semiconductor substrate, contact holes 8A and 8B are formed on the source region 5 and the drain region 6, and a metal layer as an electrode interconnection is deposited. Thereafter, this metal layer is processed to form a source electrode 9 and a drain electrode 10.
Note that FIG. 4E shows a section obtained by cutting the gate of the semiconductor device shown in FIG. 4D in a direction perpendicular to the drawing surface, in which reference numeral 13 denotes an interconnection for connecting the gate electrode 7 to another device.
FIG. 5 shows the results obtained by measuring the relationship between the threshold voltage and the gate length in a semiconductor device of this type actually manufactured by the method as described above. That is, FIG. 5 shows the relationship between the change in threshold voltage and the gate length on the basis of the threshold voltage of a semiconductor device with a gate length of 0.7 .mu.m. Referring to FIG. 5, t.sub.0 indicates the thickness of the silicon active layer 3 of the semiconductor device used in the measurement, and t.sub.1 (shown in FIG. 4E) indicates the thickness of the silicon oxide film 2 arranged below the active layer 3. Note that in FIG. 5, a curve I represents the result obtained when t.sub.0 =50 (nm) and t.sub.1 =500 (nm), and a curve II represents the result obtained when t.sub.0 =50 (nm) and t.sub.1 =200 (nm). FIG. 5 reveals that when the thickness t.sub.1 of the silicon oxide film 2 is small, the change in threshold voltage is also small if the gate channel length is shortened, and in this manner the short channel effect is suppressed. Therefore, in order to realize down scaling of a semiconductor device of this type, it is essential to decease the thickness of the silicon oxide film 2.
When the thickness t.sub.1 of the silicon oxide film decreases, however, (1) a parasitic capacitance at the drain region 6 of the semiconductor device increases. In addition, (2) in the conventional manufacturing method as described above, a thickness t.sub.2 of the insulating film located below the electrode interconnection shown in FIG. 4D decreases. This decrease in thickness results in a large increase in parasitic capacitance at interconnections for connecting semiconductor devices upon integration of the devices, and this makes it difficult to realize a high-speed operation of the semiconductor device. Note that it is clear from computations that the increase in parasitic capacitance described in item (1) above actually has no influence on realization of a high-speed operation if the thickness t.sub.1 of the silicon oxide film 2 is 10 times or more the thickness of the silicon oxide film 4 as a gate insulating film.
On the other hand, since the interconnection length in an LSI circuit reaches about 1 cm, the increase in parasitic capacitance below the interconnection has a large influence on the operating speed of the circuit. In addition, as shown in FIG. 4E, in order to form the interconnection 13 for connecting the gate electrode 7 to another device, the gate electrode must be excessively extracted onto the insulating film 2. When the thickness t.sub.1 of the insulating film 2 decreases, the parasitic capacitance of this portion becomes too large to be neglected and adversely affects the operating speed of the device.
A field-effect semiconductor device of this type, therefore, has not been put into practical use yet because it has the problems as described above as well as several good characteristics.